The present invention relates to a semiconductor memory and, more particularly, to a technique useful for a half-precharge type dynamic RAM (random-access memory).
In a dynamic RAM having a memory capacity, e.g., 1M bits, each of the memory cells has a relatively small size, and an exceedingly large number of memory cells are connected to each of the data lines. In accordance with these circumstances, the relationship between the capacity Cs of the storage capacitor of each memory cell and the floating capacity (data line capacity) Co of each data line, i.e., the ratio Cs/Co, becomes an exceeding small value. In consequence, a data signal applied to the data line from a memory cell, that is, a potential change applied to the data line in accordance with the amount of charge stored in the capacitor Cs, undesirably becomes an exceedingly minute value.
To overcome this problem, a dynamic RAM having the following arrangement is proposed in U.S. patent application Ser. No. 380,409, filed May 20, 1982, Ito et al. According to this technique, in order to ensure a desired read level from each memory cell, each data line is divided into a multiplicity of portions, that is, a memory array is divided into a multiplicity of regions in the direction of the data lines, thereby reducing the number of memory cells connected to each data line in each of the divided memory array regions and thus maintaining the ratio Cs/Co at a desired value.